Low Power Designs of VLSI Circuits


Priyabrata Pattanaik, S.K. Kamilla
Dept. of Electronics and Communication Engineering, Siksha ‘O’ Anusandhan (Deemed to be University), Odisha, India.


the total power consumption of a chip is a subject of concern in submicron technologies and leakage power should be minimized for low power designs. While considering the CMOS VLSI circuits are considered, power dissipation should be kept minimum. The battery life of applications powered by battery reduces because of high power consumption and the cooling costs and reliability of packaging is affected. This paper proposes the designing of CMOS gates by a technique of LCPMOS. It aims to the reduction of leakage current without causing dynamic power dissipation to increase. The leakage problem existing in CMOS circuits is reduced by the technique of LCPMOS. An additional leakage control transistor is involved in LCPMOS for tackling the leakage problem. A path exists from pull down network to ground and pull up, pull down networks are placed in this path for providing additional resistance and the output from this drives the leakage control transistor. Any additional monitoring and control circuitry is not required in LCPMOS technique unlike other techniques and this is the biggest advantage offered by this technique. The power dissipation is reduced in active state and the area is also limited here. The leakage power in LCPMOS is reduced upto an extent of 91.54% and it leads to the higher efficiency in terms of power dissipation and area in comparison with other techniques of power reduction.